1. Field of the Invention
The present invention generally relates to control of power supplies and voltage regulators/power converters and, more particularly, to high-resolution control of voltage regulation with digital pulse width modulation arrangements of reduced resolution and consequent reduced complexity and cost.
2. Description of the Prior Art
Many types of electrical and electronic devices require power at a substantially constant voltage, although the tolerance for voltage variation of the power supply can vary widely. However, in general, voltage regulation within a relatively small tolerance over a wide range of current loads is highly desirable even though the current load can cause variation in the voltage supplied. Efficiency of the power supply and voltage regulation arrangement is also of high importance, along with cost and complexity of the voltage regulation arrangement.
For these reasons, switching power supplies are commonly the basic design of choice over analog voltage regulators which often rely upon a significant voltage drop across the regulator at significant currents and thus generally consume significant power, whereas switching voltage regulators control the output voltage over a wide range of current loads by variation of the duty cycle during which input power is connected to the regulator circuit. Analog pulse width modulators have provided good performance but are generally more expensive, subject to noise and often require designs to be specific to particular applications. More recently, digital control has been employed in switching voltage regulators which overcome many of the drawbacks of analog controls and provide more functions more conveniently and at generally reduced cost to improve overall system performance, such as passive component reduction, noise immunity, re-programmability, communication and the like.
However, an analog power stage (e.g. a switching regulator having analog components) with a digital control loop makes system control more complicated since two quantizers, a digital pulse width modulator (DPWM) 10 and an analog to digital (A/D) converter 20 are introduced into the control loop as shown in FIG. 1. Further, the duty cycle established by the DPWM can only assume discrete values which may or may not coincide with a desired output voltage at a particular load while the resolution of the discrete duty cycle values (ΔD) ultimately determines the resolution of the regulated output voltage (ΔVo, depicted by the difference/space between dotted lines in FIGS. 2 and 3). That is, if the resolution of the DPWM is not sufficiently high for the desired output voltage to fall within a “zero error” value of A/D converter of resolution ΔVADC, depicted as a difference between solid lines, limit cycle oscillations will occur as shown in FIG. 2, as contrasted with a high resolution DPWM; the response of which is shown in FIG. 3. Such limit cycle oscillations and their amplitude and waveform, in particular, are difficult to predict but are significantly more likely to occur using a low resolution DPWM than when using a high resolution DPWM. If limit cycle oscillations occur, the amplitude of the limit cycle oscillations will exceed the resolution of the A/D converter. Thus it is clearly seen that there is a significant trade-off between cost of the A/D converter and DPWM to obtain a given degree of duty cycle resolution and the ability to reliably regulate voltage within a given voltage tolerance.
As a result of such a trade-off, many DPWM arrangements have been proposed to obtain high duty cycle resolution. For example, in a counter based DPWM, the duty cycle resolution (ΔD) is given byΔD=fsw/fclock  (1)where fsw is the switching frequency of the power stage (e.g. Q1 and Q2 of FIG. 1) and fclock is the controller system clock. Taking the buck converter arrangement of FIG. 1 as an example, the output voltage resolution (ΔV0) is given byΔVo=VIN·ΔD  (2)where VIN is the input voltage. Accordingly, it is seen from FIG. 4 that the system clock (fclock) requirement to achieve a 3 mV output voltage resolution (notwithstanding limit cycle oscillations as shown in FIG. 5) under different switching frequency (fsw) conditions generally exceed 1 GHz for common or increased fsw which is not feasible for practical implementations.